DS643 Datasheet, PDF (10/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 3: Memory and Memory Part Parameters (Cont’d)
Parameter Name
Default Value Allowable Values
C_MEM_REDUCED_DRV
0
0-3
C_MEM_REG_DIMM⁽¹⁰⁾
C_MEM_SKIP_DYNAMIC_CAL⁽⁹⁾
C_MEM_SKIP_IN_TERM_CAL⁽⁹⁾
C_MEM_TYPE
C_MMCM_EXT_LOC^(10),(16)
C_MPMC_CLK0_PERIOD_PS
0
0,1
1
0,1
1
DDR2
NOT_SET
0,1
DDR, DDR2, DDR3,
LPDDR, SDRAM
Valid MMCM_ADV
location constraint
10000
1-1000000
C_MPMC_CLK_MEM_PERIOD_PS
1
1250-6250
C_MPMC_CLK_MEM_2X_PERIOD_PS⁽⁹⁾
1
1-1000000
C_DDR2_DQSN_ENABLE⁽³⁾
C_ECC_DATA_WIDTH^(5),(6)
1
0,1
0
0, 3-8
Description
Reduced drive output enable.
(DDR/DDR2/DDR3/LPDDR) only.)
LPDDR Memory:
0 = Full
1 = Half
2 = Quarter
3 = Three Quarters
DDR/DDR2 Memory:
0 = Full
1 = Reduced
2-3 = Reserved
DDR3 Memory (Spartan-6 FPGAs):
0 = RZQ/6
1 = RZQ/7
2-3 = Reserved
DDR3 Memory (Virtex-6 FPGAs only):
0 = RZQ/7
1 = RZQ/6
2-3 = Reserved
DIMM is registered.
0 = Perform dynamic calibration (Strongly
recommended for Production silicon).
Requires ZIO I/O pin.
1 = Skip dynamic calibration.
0 = Perform input termination calibration,
Requires ZIO I/O pin.
1 = Skip input termination calibration.
(LPDDR designs should use this setting.)
Memory architecture type. Available
memory types are limited by device
architecture.
This parameter is passed to clock generator
v3.02a or greater to generate a location
constraint for the external MMCM_ADV
primitive driving the MPMC Memory clocks.
MPMC_CLK0 Period (ps). This value is
automatically calculated based on what is
connected to Port MPMC_Clk0 in XPS (for
example a clock_generator output or a
signal/port with MHS tag CLK_FREQ =
xxxx). The value can be overwritten; if set
by the user, it is not calculated.
MPMC_CLK_MEM period (ps). This value is
automatically calculated based on what is
connected to Port MPMC_Clk_Mem in XPS
(for example a clock_generator output or a
signal/port with MHS tag CLK_FREQ =
xxxx). The value can be overwritten; if set
by the user, it is not calculated.
MPMC_CLK_MEM_2X period (ps). This value
is automatically calculated based on what is
connected to Port MPMC_Clk_Mem_2x in
XPS (for example a clock_generator output
or a signal/port with MHS tag CLK_FREQ =
xxxx). The value can be overwritten; if set by
the user, it is not calculated.
Enables differential DQS (DDR2 Only).
Must be set to 0 when C_FAMILY =
“spartan3”. (Can be set to 1 for other
Spartan-3 families, such as C_FAMILY =
spartan3a, spartan3an, spartan3adsp,
spartan3e.)
Must be set to 1 when using MIG-based
Virtex-5 FPGA DDR2 PHY.
ECC Data Width (in bits).
DS643 February 22, 2013
www.xilinx.com
10
Product Specification