DS643 Datasheet, PDF (189/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
MIG PHY Supported Fmax
The Spartan-3, Virtex-4, and Virtex-5 FPGA MIG PHYs also have maximum supported frequencies that should not
be exceeded even if the MPMC is capable of meeting timing at higher clock frequencies.
Spartan-3/3A/3AN/3E/3A DSP devices can have data width limitations depending on part and package size.
Verify data width compatibility through the MIG GUI or through the “Supported Devices” section of the
device-specific, Memory Interface Solutions User Guide, in Section Three “Spartan- 3/3A/3AN/3E/3A DSP FPGA to
Memory Interfaces.” Reference Documents, page 215 contains a link to this resource.
Table 94 summarizes the maximum supported frequencies of the MIG PHYs used in the MPMC and also provides
the Application Note name that describes the MIG algorithm used in the specified FPGA family.
Table 94: MIG PHY Maximum Supported Frequencies by FPGA Family
FPGA Family
Spartan-3
Spartan-3
Spartan-3
Virtex-4
Virtex-4
Virtex-4
Virtex-4
Virtex-4
Virtex-4
Virtex-5
Virtex-5
Virtex-5
Virtex-5
Virtex-5
Virtex-5
Virtex-6 LXT
Virtex-6 LXT
Virtex-6 LXT
Virtex-6 LXT
Virtex-6 LXT
Virtex-6 LXT
Speed
Grade
-4
-5
-5
-10
-11
-12
-10
-11
-12
-1
-2
-3
-1
-2
-3
-1L
-1, -2, -3
-1L
-1
-2
-3
Memory
Type
Maximum Supported Document
PHY Memory Clock with MIG
Frequency
Algorithm
Notes
DDR/DDR2
133 MHz
XAPP454/768c
DDR/DDR2
(Component)
166 MHz
XAPP454/768c
166 MHz limited to 8-/16-/32-bit designs on
left or right sides of the parts.
DDR/DDR2
(DIMM)
133 MHz
XAPP454/768c
DDR
175 MHz
XAPP701/702
The MPMC uses Direct Clocking algorithm for
both DDR and DDR2 on Virtex-4 FPGAs.
DDR
180 MHz
XAPP701/702
DDR
185 MHz
XAPP701/702
DDR2
220 MHz
XAPP701/702
DDR2
230 MHz
XAPP701/702
DDR2
240 MHz
XAPP701/702
DDR2
266 MHz
XAPP858
DDR2
300 MHz
XAPP858
DDR2
333 MHz
XAPP858
DDR
200 MHz
XAPP851
DDR
200 MHz
XAPP851
DDR
200 MHz
XAPP851
DDR2
300 MHz
DDR2
DDR3
DDR3
DDR3
400 MHz
303 MHz
400 MHz
533 MHz
UG406
Virtex-6 FPGA maximum supported memory
clock frequency is subject to change and can
depend on additional factors. Consult MIG or
MCB documentation for the latest information.
DDR3
533 MHz
DS643 February 22, 2013
www.xilinx.com
189
Product Specification