DS643 Datasheet, PDF (9/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 3: Memory and Memory Part Parameters (Cont’d)
Parameter Name
Default Value Allowable Values
C_MEM_PART_CAS_D_FMAX^(1),(4)
x
Any Integer
C_MEM_PART_DATA_DEPTH^(1),(8)
16
1, 2, 4, 8, 16, 32, 128,
256, 512, 1024
C_MEM_PART_DATA_WIDTH⁽¹⁾
C_MEM_PART_NUM_BANK_BITS⁽¹⁾
C_MEM_PART_NUM_COL_BITS⁽¹⁾
C_MEM_PART_NUM_ROW_BITS⁽¹⁾
C_MEM_PART_TRAS⁽¹⁾
16
4, 8,16, 32, 64
2
1–4
9
1–20
13
1–20
x
Any Integer
C_MEM_PART_TRASMAX⁽¹⁾
x
Any Integer
C_MEM_PART_TRC⁽¹⁾
x
Any Integer
C_MEM_PART_TRCD⁽¹⁾
x
Any Integer
C_MEM_PART_TDQSS^(1),(2)
1
1
C_MEM_PART_TRP⁽¹⁾
C_MEM_PART_TMRD⁽¹⁾
C_MEM_PART_TRRD⁽¹⁾
C_MEM_PART_TWR⁽¹⁾
C_MEM_PART_TRFC⁽¹⁾
C_MEM_PART_TREFI⁽¹⁾
C_MEM_PART_TAL^(1),(3)
C_MEM_PART_TCCD^(1),(3)
C_MEM_PART_TWTR^(1),(3)
C_MEM_PART_TRTP^(1),(3)
C_MEM_PART_TZQINIT⁽¹¹⁾
C_MEM_PART_TZQCS⁽¹¹⁾
x
x
x
x
x
x
0
x
x
7500
0
0
Any Integer
Any Integer
Any Integer
Any Integer
Any Integer
Any Integer
0
Any Integer
Any Integer
7500
Any Integer
Any Integer
Description
Maximum memory frequency of
C_MEM_PART_CAS_D.
Discrete memory part data depth in
megabits. This parameter currently not used
and is reserved for future use.
Discrete memory part data width. Only
Spartan-6 FPGAs support a value of 4.
Number of bank bits on memory part.
Number of column bits on memory part.
Number of row bits on memory part.
tRAS - Minimum ACTIVE-to-PRECHARGE
command (ps).
tRAS - Maximum ACTIVE-to-PRECHARGE
command (ps).
tRC - Minimum ACTIVE-to-ACTIVE (same
bank) command (ps).
tRCD - Minimum ACTIVE-to-READ or
WRITE delay (ps).
tDQSS - Positive DQS latching edge to
associated clock edge (tCK). This value
should be (maximum value - minimum
value) rounded up to the nearest integer.
tRP - Minimum PRECHARGE command
period (ps).
tMRD - Minimum LOAD MODE command
cycle time (tCK). (Deprecated)
tRRD - Minimum ACTIVE bank a to ACTIVE
bank b command (ps).
tWR - Minimum write recover time (ps).
tRFC - Minimum REFRESH to ACTIVE or
REFRESH to REFRESH command interval
(ps).
tREFI - Maximum average periodic
REFRESH interval (ps).
tAL - Additive Latency desired (tCK).
tCCD - Minimum CAS# to CAS# command
delay (tCK).
tWTR - Minimum internal WRITE-to-READ
command delay (ps).
tRTP - Minimum internal READ to
PRECHARGE command delay (ps).
tZQINIT - ZQCL command: Long calibration
time for power-up or reset (tCK)
tZQCS - ZQCS command: Short calibration
time (tCK)
DS643 February 22, 2013
www.xilinx.com
9
Product Specification