DS643 Datasheet, PDF (164/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

X-Ref Target - Figure 39
Start
Address
Y Size
LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Stride
Full Video Frame Stored Linearly In External Memory
X Size
2D Transfer Region
X10911
Figure 39: 2D Transfers
The first word (Command Word 0, bits [14:0]) includes the X Size of the transfer, which is the number of consecutive
linear bytes of the transaction per line. The second word (Command Word 1, bits [31:0]) includes the direction of the
transfer and the start address. Bit 31 is, or Write_NotRead, denotes a write transaction if High and a read
transaction if Low. Bits [30:0] are the physical memory byte start address, which is the start address of the transfer.
The third word (Command Word 2, bits [23:0]) includes the Y Size of the transfer, which is the number of lines of the
transfer minus one. Figure 39 shows the Y Size as 12 lines. The value set in bits [23:0] of the third word must be
0x0000000b for this transfer.
The fourth word (Command Word 3, bits [23:0]) includes the Stride of the transfer, which is the number of bytes to
skip between the start of each line of the transfer. This is the line length (in bytes) of the 2D storage in external
memory.
VFBC Write Data Interface
The Write data interface is an asynchronous FIFO. The FIFO depth, data width, and the almost full flag are
configurable. The data width can be configured as 8, 16, 32, or 64 bits. Data is pushed onto the FIFO during the same
clock cycle as when the VFBC<Port_Num>_Wd_Write signal is active.
• The VFBC<Port_Num>_Wd_Flush signal flushes all data currently in the FIFO but keeps the current Write
command active in the command FIFO. Asserting the FIFO Flush returns the internal Read/Write FIFO
pointers to zero.
• The VFBC<Port_Num>_Wd_Reset signal flushes data in the FIFO and also flushes the Write command from
the command FIFO.
• The VFBC<Port_Num>_Wd_End_Burst signal is used only when the transfer is not a multiple of the burst size.
If the transfer ends on a boundary that is not 32-word aligned, this signal must be asserted High during the last
word transferred. Figure 40 shows a typical VFBC Write operation and provides an example of VFBC Write
Timing. The actions of the Write data interface are enumerated after Figure 40.
DS643 February 22, 2013
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Product Specification