DS643 Datasheet, PDF (42/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
SDMA Register Summary
The Service Base Address varies based on the setting of parameter C_ALL_PIMS_USE_SHARED_ADDRESSES:
• If set to 0, the Service Base Address is located at C_SDMA_CTRL<Port_Num>_BASEADDR.
• If set to 1, each port shares the same base address of C_SDMA_CTRL_BASEADDR (with no <Port_Num>
specified), and the Service Base Address for each Port is defined as follows:
• Port 0: C_SDMA_CTRL_BASEADDR + 0x0
• Port 1: C_SDMA_CTRL_BASEADDR + 0x80
• Port 2: C_SDMA_CTRL_BASEADDR + 0x100
• Port 3: C_SDMA_CTRL_BASEADDR + 0x180
• Port 4: C_SDMA_CTRL_BASEADDR + 0x200
• Port 5: C_SDMA_CTRL_BASEADDR + 0x280
• Port 6: C_SDMA_CTRL_BASEADDR + 0x300
• Port 7: C_SDMA_CTRL_BASEADDR + 0x380
Table 37 shows the SDMA registers and the PLB address offset from the Service Base Address assignment with the
allowed access to that register. These registers are available only when an SDMA interface is enabled. See SDMA
Registers, page 148 for SDMA register information.
Table 37: SDMA Registers and PLB Address Offsets from Service Base Address
PLB Address Offset from Service
Base Address Assignment
Register Name
Access
Default
Type Value (hex)
Description
Transmit Registers
0x00
TX_NXTDESC_PTR
R
00000000 TX Next Descriptor Pointer.
0x04
TX_CURBUF_ADDR
R
00000000 TX Current Buffer Address.
0x08
TX_CURBUF_LENGTH
R
00000000 TX Current Buffer Length.
0x0C
TX_CURDESC_PTR
R/W
00000000 TX Current Descriptor Pointer.
0x10
TX_TAILDESC_PTR
R/W
00000000 TX Tail Descriptor Pointer.
0x14
TX_CHNL_CTRL
R/W
00000000 TX Channel Control.
0x18
TX_IRQ_REG
R/W
00FF0000 TX Interrupt Register.
0x1C
TX_CHNL_STS
R
00000000 TX Status Register.
Receive Registers
0x20
RX_NXTDESC_PTR
R
00000000 RX Next Descriptor Pointer.
0x24
RX_CURBUF_ADDR
R
00000000 RX Current Buffer Address.
0x28
RX_CURBUF_LENGTH
R
00000000 RX Current Buffer Length.
0x2C
RX_CURDESC_PTR
R/W
00000000 RX Current Descriptor Pointer.
0x30
RX_TAILDESC_PTR
R/W
00000000 RX Tail Descriptor Pointer.
0x34
RX_CHNL_CTRL
R/W
00000000 RX Channel Control.
0x38
RX_IRQ_REG
R/W
00FF0000 RX Interrupt Register.
0x3C
RX_CHNL_STS
R
00000000 RX Status Register.
Control Registers
0x40
DMA_CONTROL_REG
R/W
0000001C DMA Control Register.
DS643 February 22, 2013
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Product Specification