DS643 Datasheet, PDF (83/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 59: Signals and Parameters per PHY Layer (Cont’d)
PHY Layer
Signals
SDRAM PHY
MPMC_Clk_Mem
MPMC_DCM_PSEN
MPMC_DCM_PSINCDEC
MPMC_DCM_PSDONE
Static PHY
MPMC_Clk_Mem
MPMC_DCM_PSEN
MPMC_DCM_PSINCDEC
MPMC_DCM_PSDONE
Parameters
C_STATIC_PHY_RDDATA_CLK_SEL
C_STATIC_PHY_RDENDELAY
C_STATIC_PHY_RDDATA_CLK_SEL
C_STATIC_PHY_RDDATA_SWAP_RISE
C_STATIC_PHY_RDENDELAY
The memory data and address signals are marked with little-endian labeling. Figure 7 and Figure 8, page 86 show
the little-endian and big-endian formats. Table 60, describes the little-endian bit and byte labeling for the data and
control signals in the external memory.
Note: Use caution with the connections to the external memory devices to avoid incorrect data and address connections. The
bit ordering used in the MPMC memory interface is reversed from the bit ordering used in the memory controllers named
plb_ddr, plb_ddr2, opb_ddr, mch_opb_ddr, and mch_opb_ddr2. The BSB can be used to create MPMC designs to
illustrate correct memory interface connections.
DS643 February 22, 2013
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Product Specification