DS643 Datasheet, PDF (64/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
X-Ref Target - Figure 5
NPI
Data Path
Read FIFO(s)
8/16/32/64/128 Bits Wide
PHY Interface
SDR Read
Data
DDR/DDR2
Data
Write
NPI
FIFO(s)
8/16/32/64/128 Bits Wide
8/16/32/64
Bits Wide
SDR Write
Data
SDR Mask
Data
X10918
Figure 5: MPMC PHY-Data Path Connection
The PHY interface converts the Double Data Rate (DDR) data from the memory into a Single Data Rate (SDR) bus
that is twice as wide as the memory width. For SDRAM, data stays the same width through the PHY.
Because the MPMC supports 8-, 16-, 32-, and 64-bit SDRAM and DDR/DDR2 memory, this results in an SDR bus
that is 8-, 16-, 32-, 64-, or 128-bits wide going to the datapath module.
The datapath module implements the per-port FIFOs used by the MPMC. Figure 6 illustrates the changes that are
made when ECC is enabled with DDR/DDR2 memory.
DS643 February 22, 2013
www.xilinx.com
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Product Specification