DS643 Datasheet, PDF (206/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
PLB PIM LUT, FF, and Slice Utilization
Table 103 through Table 105 provide the PLB PIM LUT, FF, and Slice by FPGA family, NPI width, and PLB
SUBTYPE
Table 103: PLB PIM LUT and FF Resource Utilization
FPGA Family
PLB PIM
SUBTYPE
NPI Width
Spartan-3
PLB
32
Spartan-3
PLB
64
Spartan-3
Singles
32
Spartan-3
Singles
64
Virtex-4
PLB
32
Virtex-4
PLB
64
Virtex-4
DPLB
64
Virtex-4
IPLB
64
Virtex-4
Singles
32
Virtex-4
Singles
64
Virtex-5/Virtex-6/Spartan-6
PLB
32
Virtex-5/Virtex-6/Spartan-6
PLB
64
Virtex-5/Virtex-6/Spartan-6
Singles
32
Virtex-5/Virtex-6/Spartan-6
Singles
64
LUT
Utilization
571-631
853-919
222-284
296-371
593-655
893-944
471-549
304-340
229-328
371-438
480-577
677-850
195-212
286-308
FF
Utilization
388-497
589-673
333-399
474-553
388-495
597-672
490-579
331-388
332-400
476-559
385-488
585-669
330-394
471-547
Slice Utilization
437-524
635-721
274-344
346-424
435-532
648-717
413-512
297-340
267-333
370-432
303-370
478-581
207-224
252-308
SDMA PIM LUT, FF, and Slice Resource Utilization
Table 104 provides SDMA PIM LUT, FF, and Slice resource utilization for the Spartan-3, Virtex-4, Virtex-5, and
Spartan-6 devices, as well as the values for C_SPLB_DWIDTH, C_SPLB_P2P, C_PI_RDDATA_DELAY,
C_COMPLETED_ERR_TX, and C_COMPLETED_ERR_RX.
Table 104: SDMA PIM LUT and FF Resource Utilization by FPGA Device
C_SPLB_
DWIDTH
C_SPLB_P2P
C_PI_RDDATA
_DELAY
C_COMPLETE
D_ERR_TX
C_COMPLETED
_ERR_RX
LUT
Utilization
(4-input)
FF
Utilization
Slice
Utilization
xc3s1400a-4-fg676 (Spartan-3 FPGA)
32
1
0
0
0
1881
962
1296
32
0
0
0
0
1878
1036
1323
32
0
1
0
0
1878
1036
1323
32
0
2
0
0
1924
1109
1364
32
0
2
1
0
1925
1110
1366
32
0
2
1
1
1927
1111
1368
64
0
2
1
1
1927
1111
1368
128
0
2
1
1
1927
1111
1367
xc4vfx100-10-ff1152 (Virtex-4 FPGA)
32
1
0
0
0
1957
1018
1300
32
0
0
0
0
1961
1066
1332
DS643 February 22, 2013
www.xilinx.com
206
Product Specification