DS643 Datasheet, PDF (190/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 94: MIG PHY Maximum Supported Frequencies by FPGA Family (Cont’d)
FPGA Family
Speed
Grade
Spartan-6
Spartan-6
Spartan-6
-1L, -2, -3,
-4
-1L, -2, -3,
-4
-1L
Spartan-6
-2
Spartan-6
-2
Spartan-6
-3, -4
Memory
Type
DDR
Maximum Supported
PHY Memory Clock
Frequency
200 MHz
LPDDR
200 MHz
DDR2
DDR2
DDR3
DDR2/DDR3
200 MHz
312.5 MHz (STANDARD)
333 MHz (EXTENDED)
312.5 MHz (STANDARD)
333 MHz (EXTENDED)⁽¹⁾
333 MHz (STANDARD)
400 MHz (EXTENDED)⁽¹⁾
Document
with MIG
Algorithm
UG388
Notes
Spartan-6 FPGA maximum supported
memory clock frequency is subject to change
and can depend on additional factors. Consult
MIG or MCB documentation for the latest
information.
Notes:
1. Production grade Spartan-6 devices using DDR3 can be operated in EXTENDED mode for the full V_CCINT voltage range. For DDR2,
EXTENDED mode requires improved regulation for V_CCINT voltage.
MPMC Optimization
This section provides information about optimizing and tuning MPMC timing, performance, and size. It is
recommended that you begin with creating a stable working MPMC system using default parameters settings and
system configurations when possible. For example, start with an MPMC system created by the BSB tool in XPS.
After establishing a working system, the following information can be used to fine tune the MPMC and experiment
with different settings.
MPMC Performance Optimization
The following list identifies possible ways to improve MPMC performance:
• Increase clock frequency as much as possible. Higher clock frequency increases throughput and can lower
latency. It is useful to have the flexibility in the board to set the clock frequency to match the Fmax of the
MPMC. For example, if a system has a fixed 100 MHz oscillator, the memory might have to run at 100 or
200 MHz. If the Fmax of the MPMC is 145 MHz, having the ability to install a 145 MHz oscillator is ideal for
maximizing MPMC performance.
• Latency can be reduced by disabling pipeline stages. Disabling pipeline stages has the trade-off that it might
degrade timing. In some cases you could be running at a memory clock frequency well below the Fmax of the
MPMC in which case disabling pipelines would not cause timing failures. It is recommended that you first get
your system working in the default case where all pipeline stages are on and then experiment with disabling
as many pipeline stages as possible while timing is still met. For example, the following parameters can be
used to reduce latency in the MPMC core:
PARAMETER C_WR_DATAPATH_TML_PIPELINE = 0
PARAMETER C_ARB_PIPELINE = 0
PARAMETER C_PI<Port_Num>_ADDRACK_PIPELINE = 0
PARAMETER C_PI<Port_Num>_RD_FIFO_MEM_PIPELINE = 0
PARAMETER C_PI<Port_Num>_RD_FIFO_APP_PIPELINE = 0
PARAMETER C_PI<Port_Num>_WR_FIFO_MEM_PIPELINE = 0
PARAMETER C_PI<Port_Num>_WR_FIFO_APP_PIPELINE = 0
Note: Some FIFO pipeline parameters must be the same value across all ports. See Memory and Memory Part
Parameters, page 7 for more information
DS643 February 22, 2013
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190
Product Specification