DS643 Datasheet, PDF (72/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
The IP Interrupt Status register (IPIS) is the interrupt capture register for the ECC logic. Table 50 describes the bit
values for the IPIS.
Table 50: IPIS Register Bit Definitions
Bit(s)
0:28
29
30
31
Name
PE_IS
DE_IS
SE_IS
Core
Access
R/TOW⁽¹⁾
R/TOW⁽¹⁾
R/TOW⁽¹⁾
Reset
Value
Description
Reserved
Parity Field Bit Error Interrupt Status: Indicates a parity field bit error has occurred
during the memory data transaction. In the ECC module, parity field bit errors are
corrected as data is read from memory. This interrupt is for system monitoring only
0 _{and does not indicate corrupt data.}
0 = Parity field bit error count is less than C_ECC_PEC_THRESHOLD.
1 = Parity field bit error count is more than C_ECC_PEC_THRESHOLD.
Double-Bit Error Interrupt Status: Indicates a double-bit data error has occurred
during the memory transaction. In the ECC module, double-bit errors can be
detected, but not corrected. When this interrupt is asserted, the data read from
0 _{memory is not valid.}
0 = Double-bit error count is less than C_ECC_DEC_THRESHOLD.
1 = Double-bit error count is more than C_ECC_DEC_THRESHOLD.
Single-Bit Error Interrupt Status: Indicates a single-bit error has been detected
during the memory transaction. In the ECC module, single-bit errors are detected
and corrected. This interrupt is for system monitoring only and does not indicate
0 _{corrupt data.}
0 = Single-bit error count is less than C_ECC_SEC_THRESHOLD.
1 = Single-bit error count is more than C_ECC_SEC_THRESHOLD.
Notes:
1. TOW is Toggle On Write.
Writing a 1 to a bit position within the register causes the corresponding bit position in the register to toggle.
IP Interrupt Enable Register
The IP Interrupt Enable register (IPIE) has an enable bit for each defined bit of the IP Interrupt Status register.
Table 51 describes the bit values for the ECC IPIE.
Table 51: IPIE Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0:28
Reserved
Parity Field Bit Error Interrupt Enable: Enables assertion of the interrupt
for indicating parity field bit errors have occurred.
29
PE_IE
R/W
0 _{0 = Disabled}
1 = Enabled
Double-bit Error Interrupt Enable: Enables assertion of the interrupt for
30
DE_IE
R/W
0 ^{indicating double-bit data errors have occurred.}
0 = Disabled
1 = Enabled
Single-bit Error Interrupt Enable: Enables assertion of the interrupt for
indicating single-bit data errors have occurred.
31
SE_IE
R/W
0 _{0 = Disabled}
1 = Enabled
DS643 February 22, 2013
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