DS643 Datasheet, PDF (124/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
XCL Configuration Options
Dual XCL Buses on One XCL PIM
For resource optimization when connecting two XCL buses to the MPMC it is recommended that the MPMC
parameter, C_XCL<Port_Num>_B_IN_USE, is set to 1. This enables a second XCL bus to connect to the MPMC by the
bus that is designated as XCL<Port_Num>_B, while only consuming one of the available ports on the MPMC. For
example, if Port 0 of the MPMC is configured as XCL and C_XCL0_B_IN_USE = 1, then connect the MicroBlaze
processor IXCL bus to MPMC XCL0 bus. Similarly, connect the MicroBlaze processor DXCL bus to the MPMC
XCL0_B bus. The XCL PIM internally arbitrates between the two buses with priority given to the XCL0_B bus if they
are both idle and receive XCL requests at the same time. If both ports are requesting continuously, round-robin
arbitration goes between the two ports to avoid starvation, which allows you to connect up to 16 XCL buses to the
MPMC. The relationship between the IXCL and DXCL transactions on MicroBlaze processor results in a minimal
performance impact. If you are using custom XCL masters that have high bandwidth requirements, it might be
more suitable to use two separate XCL PIMs.
When C_XCL<Port_Num>_B_IN_USE is set to 1, three additional parameters are available to be set:
• C_PIM<Port_Num>_B_SUBTYPE
• C_XCL<Port_Num>_B_LINESIZE
• C_XCL<Port_Num>_B_WRITEXFER
These parameters function identically to the parameters of the same name with a suffix of _B, consequently they are
not explicitly discussed. The bus interface XCL<Port_Num>_B becomes visible as a valid XCL bus interface target
when dual XCL mode is enabled.
XCL PIM Subtypes
The C_PIM<Port_Num>_SUBTYPE parameter is automatically detected when connected to a MicroBlaze processor.
The subtype settings of IXCL, IXCL2, DXCL, and DXCL2 change the operation of XCL slightly to improve
maximum frequency and reduce latency when connected to the MicroBlaze processor.
Table 67 provides a summary of the differences between the subtypes:
Table 67: XCL Supported Features by Subtype
XCL
SUBTYPE
XCL
IXCL
DXCL
IXCL2
DXCL2
Supports
Target Word
First Read
Transactions
Yes
Yes
Yes
No
No
Supports
Word Write
Operations
Yes⁽¹⁾
No
Yes
No
Yes
Supports
Supports Supports Supports
Cacheline Write Line Size Line Size Standard FSL
Operations
1 & 16
4 & 8 Handshaking
Yes⁽²⁾
No
No
No
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
No
No
Yes
No
Notes:
1. Valid if C_XCL<Port_Num>WRITEXFER = 1
2. Valid If C_XCL<Port_Num>_WRITEXFER = 2
DS643 February 22, 2013
www.xilinx.com
124
Product Specification