DS643 Datasheet, PDF (57/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Write Requests
Addresses corresponding to a Write request must be aligned to the size of the requested transfer as:
• Word transfers (32-bit NPI only) are 4-byte aligned
• Double-word transfers (64-bit NPI only) are 8-byte aligned
• 4-word cache-line transfers are 16-byte aligned
• 8-word cache-line transfers are 32-byte aligned
• 16-word burst transfers are 64-byte aligned
• 32-word burst transfers are 128-byte aligned
• 64-word burst transfers are 256-byte aligned
(Not supported in all configurations. See Restrictions on 64-Word Burst Transfers, page 173 for more
information.)
Data Path
The MPMC datapath comprises the following:
• Supported Data Widths
• FIFO Types
• Read Word Address
• Data Path Pipelines
Supported Data Widths
The MPMC supports NPI data widths of 32 and 64 bits. In the discussion of data widths, “32-bit NPI” refers to an
NPI data width of 32 bits, “64-bit NPI” refers to an NPI data width of 64 bits, and “NPI” refers to either 32- or 64-bit
data widths.
The datapath supports SDRAM, DDR, and DDR2 memories that have total physical data widths of 8, 16, 32, and 64
bits. For Virtex-6 FPGAs, the datapath limits the physical data widths of DDR2 and DDR3 memories to 8, 16, or 32
bits. Virtex-6 FPGA DDR2 or DDR3 designs do not support 64-bit physical memory.
FIFO Types
In MPMC, you can select either block RAM or 16-bit Shift register Lookup (SRL) table FIFOs. Generally, a block
RAM FIFO gives the best performance because the timing is better and the FIFO depth is larger and does not create
stalls in the datapath due to a full FIFO condition. The Write block RAM FIFO does not assert the
PIM<Port_Num>_WrFIFO_AlmostFull which can simplify the design of PIMs also because the PIM does not need
to monitor the almost full flag dynamically. The PIM is therefore required to ensure that a block RAM FIFO never
reaches a write FIFO full state. The block RAM FIFO also provides better timing than an SRL FIFO which might
allow for a higher Fmax. This is especially true for Spartan-3 FPGAs where the timing on the SRL primitive is
significantly worse than the timing on block RAM primitive timing. However, in some cases, an SRL FIFO can
improve system timing versus a block RAM FIFO when the MPMC has a large number of ports and routing to the
block RAMs results in excessive net delays.
Some configurations of MPMC might require more block RAMs than are available on a particular device, in which
case the SRL FIFOs can be used. Additionally particular applications or system configurations can use a significant
number of block RAMs, leaving few resources for the MPMC.
DS643 February 22, 2013
www.xilinx.com
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Product Specification