C8051F970-A-GM Datasheet, PDF (99/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Low power idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared. But the interrupt only causes the
device to switch from low power idle mode to low power active mode. To return to normal active mode, the
CLKMODE register should be reset to 0x00. The pending interrupt will be serviced and the next instruction to be
executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the Idle
Mode Select bit. If low power idle mode is terminated by an internal or external reset, the CIP-51 performs a normal
sequence and begins program execution at address 0x0000.
If enabled, the watchdog timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the
low power idle mode. This feature protects the system from an unintended permanent shutdown in the event of an
inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to
entering the low power idle mode if the WDT was initially configured to allow this operation. This provides the
opportunity for additional power savings, allowing the system to remain in the low power idle mode indefinitely,
waiting for an external stimulus to wake up the system. Refer to "27.6. PCA Watchdog Timer Reset" on page 326
for more information on the use and configuration of the WDT.
16.8. Configuring Wakeup Sources
Before placing the device in a low power mode, one or more wakeup sources should be enabled so that the device
does not remain in the low power mode indefinitely. For idle and low power idle modes, this includes enabling any
interrupt. For stop mode, this includes enabling any reset source or relying on the RST pin to reset the device.
No wake-up source is needed for low power active mode. Firmware needs to set the CLKMODE register to 0x00 to
return to normal active mode
Wake-up sources for suspend and sleep modes are configured through the PMU0CF register. Wake-up sources
are enabled by writing 1 to the corresponding wake-up source enable bit. Wake-up sources must be re-enabled
each time the device is placed in suspend or sleep mode, in the same write that places the device in the low power
mode.
The reset pin is always enabled as a wake-up source. On the falling edge of RST the device will be awaken from
sleep mode. The device must remain awake for more than 15 µs in order for the reset to take place.
16.9. Determining the Event that Caused the Last Wakeup
When waking from Idle or Low Power Idle mode, the CPU will vector to the interrupt which caused it to wake up.
When waking from stop mode, the RSTSRC register may be read to determine the cause of the last reset.
Upon exit from suspend or sleep mode, the wake-up flags in the PMU0CF and PMU0FL registers can be read to
determine the event which caused the device to wake up. After waking up, the wakeup flags will continue to be
updated if any of the wake-up events occur. Wakeup flags are always updated, even if they are not enabled as
wake-up sources.
All wakeup flags enabled as wakeup sources in PMU0CF and PMU0FL must be cleared before the device can
enter suspend or sleep mode. After clearing the wakeup flags, each of the enabled wakeup events should be
checked in the individual peripherals to ensure that a wakeup event did not occur while the wakeup flags were
being cleared.
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