C8051F970-A-GM Datasheet, PDF (187/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
21. Direct Memory Access (DMA0)
An on-chip direct memory access (DMA0) is included on the C8051F97x devices. The DMA0 subsystem allows
unattended variable-length data transfers between XRAM and peripheral SFR registers without CPU intervention.
During DMA0 operation, the CPU is free to perform some other tasks. In order to save total system power
consumption, the CPU and Flash can be powered down. DMA0 improves the system performance and efficiency
with high data throughput peripherals.
DMA0 contains seven independent channels, common control registers, and a DMA0 engine (see Figure 21.1).
Each channel includes a register that assigns a peripheral to the channel, a channel control register, and a set of
SFRs that include XRAM address information and SFR address information used by the channel during a data
transfer. The DMA0 architecture is described in detail in “21.1. DMA0 Architecture” .
The DMA0 in C8051F97x devices supports two peripherals: MAC0 and I2C0. Peripherals with DMA0 capability
should be configured to work with the DMA0 through their own registers. The DMA0 provides up to seven
channels, and each channel can be configured for one of eight possible data transfer functions:
XRAM to MAC A registers (MAC0AH, MAC0AL).
XRAM to MAC B registers (MAC0BH, MAC0BL).
XRAM to MAC accumulator registers (MAC0ACCn).
MAC accumulator registers (MAC0ACCn) to XRAM.
I2C Slave 0 received data register (I2C0DIN) to XRAM.
XRAM to I2C Slave 0 transmit data register (I2C0DOUT).
Functions 5 and 6 are mutually exclusive.
The DMA0 subsystem signals the MCU through a set of interrupt service routine flags. Interrupts can be generated
when the DMA0 transfers half of the data length or full data length on any channel.
Channel 6
MAC A request
MAC B request
MAC C input request
MAC C output request
I2C transmit request
I2C receive request
Peripheral assignment -
DMA0nCF[2:0]
Channel 1
Channel 0
Channel
Control
Channel memory
interface config
DMA0nBAH
DMA0nBAL
DMA0nCF
DMA0nAOH DMA0nAOL
DMA0nSZH
DMA0nSZL
DMA
ENGINE
Common
Control/
Status
DMA0SEL
DMA0BUSY
DMA0MINT
DMA0INT
DMA0EN
Figure 21.1. DMA0 Block Diagram
Internal
DMA
bus
control
188
Rev 1.0