C8051F970-A-GM Datasheet, PDF (343/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
29.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I²C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I²C-Bus Specification—Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
29.2. SMBus Configuration
Figure 29.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage between
3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. However, the maximum
voltage on any port pin must conform to the electrical characteristics specifications. The bi-directional SCL (serial
clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or
similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the
SCL and SDA lines, so that both are pulled high (recessive state) when the bus is free. The maximum number of
devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and
1000 ns, respectively.
VDD = 3.6V
VDD = 3V
VDD = 3.8V
VDD = 3V
Master
Device
Slave
Device 1
Slave
Device 2
SDA
SCL
Figure 29.2. Typical SMBus Configuration
29.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver
(WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device
initiates both types of data transfers and provides the serial clock pulses on SCL. The SMBus interface may
operate as a master or a slave, and multiple master devices on the same bus are supported. If two or more
masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master
always winning the arbitration. It is not necessary to specify one device as the Master in a system; any device who
transmits a START and a slave address becomes the master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit slave
address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are received (by a
master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see Figure 29.3). If the receiving
device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a
high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic
1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
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