C8051F970-A-GM Datasheet, PDF (438/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 33.6. PCA0CPM0: PCA Channel 0 Capture/Compare Mode 0
Bit
7
6
5
4
3
2
1
0
Name PWM16 ECOM
CAPP
CAPN
MAT
TOG
PWM
ECCF
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0xDA
Table 33.9. PCA0CPM0 Register Bit Descriptions
Bit
Name
Function
7
PWM16 Channel 0 16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8 to 11-bit PWM selected.
1: 16-bit PWM selected.
6
ECOM Channel 0 Comparator Function Enable.
This bit enables the comparator function.
5
CAPP Channel 0 Capture Positive Function Enable.
This bit enables the positive edge capture capability.
4
CAPN Channel 0 Capture Negative Function Enable.
This bit enables the negative edge capture capability.
3
MAT Channel 0 Match Function Enable.
This bit enables the match function. When enabled, matches of the PCA counter with a
module's capture/compare register cause the CCF0 bit in the PCA0MD register to be set
to logic 1.
2
TOG Channel 0 Toggle Function Enable.
This bit enables the toggle function. When enabled, matches of the PCA counter with the
capture/compare register cause the logic level on the CEX0 pin to toggle. If the PWM bit
is also set to logic 1, the module operates in Frequency Output Mode.
1
PWM Channel 0 Pulse Width Modulation Mode Enable.
This bit enables the PWM function. When enabled, a pulse width modulated signal is out-
put on the CEX0 pin. 8 to 11-bit PWM is used if PWM16 is cleared to 0; 16-bit mode is
used if PWM16 is set to 1. If the TOG bit is also set, the module operates in Frequency
Output Mode.
0
ECCF Channel 0 Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCF0) interrupt.
0: Disable CCF0 interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCF0 is set.
Rev 1.0
439