C8051F970-A-GM Datasheet, PDF (249/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 24.3. CLKMODE: Clock Mode
Bit
7
6
5
4
Name
Reserved
Type
R
Reset
0
0
0
0
SFR Page = 0x0; SFR Address: 0xF7
3
2
1
0
LPME
ECSR
FCAM
RW
RW
RW
0
0
0
0
Bit
Name
Function
7:3
Reserved Must write reset value.
2
LPME Low Power Mode Enable.
Setting this bit allows the device to enter low power active/idle mode. PCLKEN settings
are only enabled when this bit is set.
1
ECSR Clock Request Enable.
When this bit is set, the source clocks will only be requested when an incoming request
is active or a peripheral clock is enabled.
0
FCAM Force Clock Tree Enable.
When this bit is set, clock gating will only be performed in idle mode. This allows a user
to have complete access to all SFRs in active mode, but still get the benefits of clock gat-
ing in idle mode.
250
Rev 1.0