C8051F970-A-GM Datasheet, PDF (349/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Table 29.3. Sources for Hardware Changes to SMB0CN
Bit
Set by Hardware When:
Cleared by Hardware When:
A START has been generated.
Must be cleared by software.
Lost arbitration.
A byte has been transmitted and an ACK/
NACK received.
SI
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
29.4.5. Hardware Slave Address Recognition
The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an ACK
without software intervention. Automatic slave address recognition is enabled by setting the EHACK bit in register
SMB0ADM to 1. This will enable both automatic slave address recognition and automatic hardware ACK
generation for received bytes (as a master or slave). More detail on automatic hardware ACK generation can be
found in Section 29.4.4.2.
The registers used to define which address(es) are recognized by the hardware are the SMBus Slave Address
register and the SMBus Slave Address Mask register. A single address or range of addresses (including the
General Call Address 0x00) can be specified using these two registers. The most-significant seven bits of the two
registers are used to define which addresses will be ACKed. A 1 in a bit of the slave address mask SLVM enables
a comparison between the received slave address and the hardware’s slave address SLV for that bit. A 0 in a bit of
the slave address mask means that bit will be treated as a “don’t care” for comparison purposes. In this case, either
a 1 or a 0 value are acceptable on the incoming slave address. Additionally, if the GC bit in register SMB0ADR is
set to 1, hardware will recognize the General Call Address (0x00). Table 29.4 shows some example parameter
settings and the slave addresses that will be recognized by hardware under those conditions.
Table 29.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address
SLV
0x34
0x34
0x34
0x34
0x70
Slave Address Mask
SLVM
0x7F
0x7F
0x7E
0x7E
0x73
GC bit Slave Addresses Recognized by
Hardware
0
0x34
1
0x34, 0x00 (General Call)
0
0x34, 0x35
1
0x34, 0x35, 0x00 (General Call)
0
0x70, 0x74, 0x78, 0x7C
29.4.6. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt
to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface
may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is
located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in.
SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from
master transmitter to slave receiver is made with the correct data or address in SMB0DAT.
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