C8051F970-A-GM Datasheet, PDF (360/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Table 29.8. SMB0CN Register Bit Descriptions
Bit
Name
Function
0
SI
SMBus Interrupt Flag.
This bit is set by hardware to indicate that the current SMBus state machine operation
(such as writing a data or address byte) is complete. While SI is set, SCL is held low and
SMBus is stalled. SI must be cleared by firmware. Clearing SI initiates the next SMBus
state machine operation.
Rev 1.0
361