C8051F970-A-GM Datasheet, PDF (290/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 26.6. P0MDIN: Port 0 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
B7
B6
B5
B4
B3
B2
B1
B0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
1
1
1
1
1
1
1
1
SFR Page = 0xF; SFR Address: 0xEC
Table 26.9. P0MDIN Register Bit Descriptions
Bit
Name
Function
7
B7
Port 0 Bit 7 Input Mode.
0: P0.7 pin is configured for analog mode.
1: P0.7 pin is configured for digital mode.
6
B6
Port 0 Bit 6 Input Mode.
0: P0.6 pin is configured for analog mode.
1: P0.6 pin is configured for digital mode.
5
B5
Port 0 Bit 5 Input Mode.
0: P0.5 pin is configured for analog mode.
1: P0.5 pin is configured for digital mode.
4
B4
Port 0 Bit 4 Input Mode.
0: P0.4 pin is configured for analog mode.
1: P0.4 pin is configured for digital mode.
3
B3
Port 0 Bit 3 Input Mode.
0: P0.3 pin is configured for analog mode.
1: P0.3 pin is configured for digital mode.
2
B2
Port 0 Bit 2 Input Mode.
0: P0.2 pin is configured for analog mode.
1: P0.2 pin is configured for digital mode.
1
B1
Port 0 Bit 1 Input Mode.
0: P0.1 pin is configured for analog mode.
1: P0.1 pin is configured for digital mode.
0
B0
Port 0 Bit 0 Input Mode.
0: P0.0 pin is configured for analog mode.
1: P0.0 pin is configured for digital mode.
Note: Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled.
Rev 1.0
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