C8051F970-A-GM Datasheet, PDF (30/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
2.7. Digital Peripherals
2.7.1. Direct Memory Access (DMA0)
The DMA0 module on C8051F97x devices enables autonomous data movement between XRAM and select
peripherals. The key features of the DMA module are:
Supports 7 channels.
Separate full-length and mid-point transfer interrupts for each channel.
Options for big or little endian transfers.
Directly supports the I2C Slave 0 and MAC0 modules.
2.7.2. Multiply and Accumulate (MAC0)
The C8051F97x devices include a multiply and accumulate engine which can be used to speed up many
mathematical operations. The MAC0 module has the following key features:
Single cycle operation.
Multiply-accumulate or multiply only.
Support for integer or fractional operations.
Support for signed or unsigned operations.
Rounding with saturation.
Auto-increment or constant A and/or B registers.
Logical 1-bit or multiple bit shift of accumulator left or right.
Negation of accumulator, A, and/or B registers.
DMA support for repetitive operations on large arrays of data.
Signed and unsigned alignment (right shift in bytes) of accumulator result.
2.8. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset
state, the following occur:
The core halts program execution.
Module registers are initialized to their defined reset values unless the bits reset only with a power-on
reset.
External port pins are forced to a known state.
Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a
power-on reset. The contents of RAM are unaffected during a reset; any previously stored data is preserved as
long as power is not lost.
The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For
VDD Supply Monitor resets, the RST pin is driven low until the device exits the reset state.
On exit from the reset state, the program counter (PC) is reset, the system clock defaults to the internal low-power
oscillator, and the Watchdog Timer is enabled. Program execution begins at location 0x0000.
2.9. Unique Identifier
Each device contains a 128-bit unique identifier (UID) at the last 16 bytes of XRAM. This value is reloaded after
each device reset, and firmware can overwrite the memory area during operation, if desired.
2.10. On-Chip Debugging
The C8051F97x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming
and in-system debugging with the production part installed in the end application. The C2 interface uses a clock
signal (C2CK) and a bidirectional C2 data signal (C2D) to transfer information between the device and a host sys-
tem. See the C2 Interface Specification for details on the C2 protocol.
30
Rev 1.0