C8051F970-A-GM Datasheet, PDF (153/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 18.11. CS0MD3: Capacitive Sense 0 Mode 3
Bit
7
6
5
Name
Reserved
Type
RW
Reset
0
0
0
SFR Page = 0x0; SFR Address: 0xBF
4
3
CS0RP
RW
0
0
2
1
0
CS0LP
RW
0
0
0
Bit
Name
Function
7:5
Reserved Must write reset value.
4:3
CS0RP CS0 Ramp Selection.
These bits are used to compensate CS0 conversions for circuits requiring slower ramp
times. For most touch-sensitive switches, the default (fastest) value is sufficient.
00: Ramp time is less than 1.5 us.
01: Ramp time is between 1.5 us and 3 us.
10: Ramp time is between 3 us and 6 us.
11: Ramp time is greater than 6 us.
2:0
CS0LP CS0 Low Pass Filter Selection.
These bits set the internal corner frequency of the CS0 low-pass filter. Higher values of
CS0LP result in a lower internal corner frequency.
For most touch-sensitive switches, the default setting of 000b should be used. If the
CS0RP bits are adjusted from their default value, the CS0LP bits should normally be set
to 001b. Settings higher than 001b will result in attenuated readings from the CS0 mod-
ule and should be used only under special circumstances.
Rev 1.0
153