C8051F970-A-GM Datasheet, PDF (329/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
28.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
28.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used
to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master
and an input when SPI0 is operating as a slave. Data is transferred most-significant bit first. When configured as a
master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire mode.
28.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is
used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a
master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit first. The MISO pin
is placed in a high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as
a slave that is not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift
register.
28.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to
synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this
signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is not selected
(NSS = 1) in 4-wire slave mode.
28.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the
SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select signal
is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-point
communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled
as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a master, a 1-to-
0 transition of the NSS signal disables the master function of SPI0 so that multiple master devices can be
used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an output.
The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration should only
be used when operating SPI0 as a master device.
See Figure 28.2, Figure 28.3, and Figure 28.4 for typical connection diagrams of the various operational modes.
Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire slave
mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be mapped to a pin
on the device.
330
Rev 1.0