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C8051F970-A-GM Datasheet, PDF (97/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash
C8051F97x
16.3. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter stop mode as soon as the instruction that
sets the bit completes execution. In Stop mode the precision internal oscillator and CPU are stopped; the state of
the low power oscillator and the external oscillator circuit is not affected. Each analog peripheral (including the
external oscillator circuit) may be shut down individually prior to entering stop mode. Stop mode can only be
terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and begins
program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the stop mode. The
Missing Clock Detector should be disabled if the CPU is to be put to in stop mode for longer than the MCD timeout.
Stop mode is a legacy 8051 power mode; it will not result in optimal power savings. Sleep or suspend mode will
provide more power savings if the MCU needs to be inactive for a long period of time.
Note: To ensure the MCU enters a low power state upon entry into stop mode, the one-shot circuit should be enabled by
clearing the BYPASS bit (FLSCL.6).
16.4. Suspend Mode
Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal
oscillators disabled. All digital logic (timers, communication peripherals, interrupts, CPU, etc.) stops functioning
until one of the enabled wake-up sources occurs.
The following wake-up sources can be configured to wake the device from suspend mode:
SmaRTClock oscillator fail
SmaRTClock alarm
Port Match event
I2C0 address match
CS0 comparator threshold event
Note: Upon wake-up from suspend mode, PMU0 requires two system clocks in order to update the PMU0CF wake-up flags.
All flags will read back a value of '0' during the first two system clocks following a wake-up from suspend mode.
The state of the wake-up source's interrupt indicator bit is not valid until 6 clock cycles after the device returns from
suspend mode. If firmware needs to check a wake-up source's interrupt flag, firmware should insert instructions to wait 6
clock cycles between the call to enter suspend mode and the instruction that polls the interrupt flag.
In addition, a noise glitch on RST that is not long enough to reset the device will cause the device to exit suspend.
In order for the MCU to respond to the pin reset event, software must not place the device back into suspend mode
for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-up was due to a falling edge
on the RST pin. If the wake-up source is not due to a falling edge on RST, there is no time restriction on how soon
software may place the device back into suspend mode. A 4.7 k pullup resistor to VDD is recommend for RST to
prevent noise glitches from waking the device.
16.5. Sleep Mode
Setting the Sleep Mode Select bit (PMU0CF.6) turns off the internal 1.8 V regulator (VREG0) and switches the
power supply of all on-chip RAM to the VDD pin (see Figure 16.2). Power to most digital logic on the chip is
disconnected; only PMU0 and the SmaRTClock remain powered. All analog peripherals (ADC0, External
Oscillator, etc.) should be disabled prior to entering sleep mode.
GPIO pins configured as digital outputs will retain their output state during sleep mode. They will maintain the same
current drive capability in sleep mode as they have in normal active mode.
GPIO pins configured as digital inputs can be used during sleep mode as wakeup sources using the port match
feature. They will maintain the same input level specifications in sleep mode as they have in normal active mode.
C8051F97x devices support a wakeup request for external devices. Upon exit from sleep mode, the wake-up
request signal is driven low, allowing other devices in the system to wake up from their low power modes. The
wakeup request signal is low when the MCU is awake and high when the MCU is asleep.
Rev 1.0
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