C8051F970-A-GM Datasheet, PDF (421/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
33.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the
16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H
into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. Reading the PCA0L
Register first guarantees an accurate reading of the entire 16-bit PCA0 counter. Reading PCA0H or PCA0L
does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD register select the timebase for the
counter/timer as shown in Table 33.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to
logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1
enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software. Clearing the CIDL bit in the
PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle mode.
Table 33.1. PCA Timebase Input Options
CPS2 CPS1 CPS0
Timebase
0
0
0 _{System clock divided by 12}
0
0
1 _{System clock divided by 4}
0
1
0 Timer 0 overflow
0
1
1 _{High-to-low transitions on ECI (max rate = system clock divided by 4)}
1
0
0 _{System clock}
1
0
1 External oscillator source divided by 8¹
1
1
0 _{SmaRTClock oscillator source divided by 8}²
1
1
1 _Reserved
Notes:
1. External oscillator source divided by 8 is synchronized with the system clock.
2. SmaRTClock oscillator source divided by 8 is synchronized with the system clock.
IDLE
PCA0MD
C WW
I DD
DT L
L EC
K
CCCE
PPPC
SSSF
210
PCA0CN
CC
CCC
FR
CCC
FFF
210
SYSCLK/12
000
SYSCLK/4
001
Tim er 0 O verflow
010
ECI
011
SYSCLK
100
External Clock/8
101
Sm aRTClock/8
110
PCA0L
read
Snapshot
R e g is te r
To SFR Bus
0
PCA0H
PCA0L
O verflow
To PCA Interrupt System
1
CF
To PCA Modules
Figure 33.2. PCA Counter/Timer Block Diagram
422
Rev 1.0