C8051F970-A-GM Datasheet, PDF (91/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
14. External Interrupts (INT0 and INT1)
The C8051F97x device family includes two external digital interrupt sources (INT0 and INT1), with dedicated
interrupt sources (up to 16 additional I/O interrupts are available through the port match function). As is the case on
a standard 8051 architecture, certain controls for these two interrupt sources are available in the Timer0/1
registers. Extensions to these controls which provide additional functionality on C8051F97x devices are available
in the IT01CF register. INT0 and INT1 are configurable as active high or low, edge or level sensitive. The IN0PL
and IN1PL bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON select level or
edge sensitive. The table below lists the possible configurations.
IT0
IN0PL
INT0 Interrupt
1
0 Active low, edge sensitive
1
1 Active high, edge sensitive
0
0 Active low, level sensitive
0
1 Active high, level sensitive
IT1
IN1PL
INT1 Interrupt
1
0 Active low, edge sensitive
1
1 Active high, edge sensitive
0
0 Active low, level sensitive
0
1 Active high, level sensitive
INT0 and INT1 are assigned to port pins as defined in the IT01CF register. Note that INT0 and INT1 Port pin
assignments are independent of any crossbar assignments. INT0 and INT1 will monitor their assigned port pins
without disturbing the peripheral that was assigned the port pin via the crossbar. To assign a port pin only to INT0
and/or INT1, configure the crossbar to skip the selected pin(s).
IE0 and IE1 in the TCON register serve as the interrupt-pending flags for the INT0 and INT1 external interrupts,
respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-
pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level
sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding
polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must
hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before
execution of the ISR completes or another interrupt request will be generated.
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