C8051F970-A-GM Datasheet, PDF (370/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
30.5. I2C Transfer Modes
The I2CSLAVE0 interface may be operating in either I²C Write or I²C Read mode. Data transfers can also be
controlled by DMA, depending on whether a DMA channel has selected I²C Read or Write as a data transfer
function. The following sub-sections describe in detail the setting and clearing of various status bits in the
I2C0STAT register during different modes of operations. In all modes, the I2CSLAVE0 peripheral performs clock
stretching automatically on every SCL falling edge associated with the ACK or NACK bit.
30.5.1. I2C Write Sequence (CPU mode)
Figure 30.5 shows the details of how the I2C0STAT status bits change during an I²C Write data transfer.
I2C0 module – CPU mode – clock stretch – Write
1
Sleep
Active
2
S SLA W A
3
DB0 A
DB1 A
DB2 A Sr SLA W A
45
DB3 N P
xa
b
c
d
e
x
f
gh
1 SLA+W wakes CPU from sleep mode. Automatic ACK if BUSY was 0.
2 INT generated – starting clock stretch. CPU clears I2C0INT, which releases SCL
3 CPU fetches DB0 from I2C0DIN; ACK bit cleared to ‘0’; CPU clears I2C0INT, which releases SCL
S = START
P = STOP
A = ACK
N = NACK
R = Read
W = Write
Sr = repeated START
Shaded blocks are
generated by Slave
device
4 Slave doesn’t care whether it generates NACK or ACK. State machine response is the same for both.
5 Stop bit (P) generates interrupt. No Clock Stretch. CPU clears I2C0INT
No int x I2C0STAT = x1001000 at 8^th SCL rising edge
I2C0 int a I2C0STAT = x1101010; CPU clears START and I2C0INT
I2C0 int b I2C0STAT = x1100010; CPU fetches DB0 from I2C0DIN and clears I2C0INT
I2C0 int c I2C0STAT = x1100010; CPU fetches DB1 from I2C0DIN and clears I2C0INT
I2C0 int d I2C0STAT = x1100010; CPU fetches DB2 from I2C0DIN and clears I2C0INT
I2C0 int e I2C0STAT = x0100000; CPU services end of transaction and clears I2C0INT
I2C0 int f I2C0STAT = x1101010; CPU clears START and I2C0INT; CPU writes ‘1’ to BUSY to NACK future data transfers
I2C0 int g
I2C0STAT = x1110010; CPU fetches DB3 from I2C0DIN and clears I2C0INT, NACK; CPU writes ‘0’ to BUSY to ACK future
data transfers
I2C0 int h I2C0STAT = x0100100; CPU clears STOP and I2C0INT
* At a, b, c, d, f, g : Bits are set/cleared at 9^th SCL falling edge. CPU clears I2C0INT to release SCL
Figure 30.5. Typical I²C Write Sequence in CPU Mode
Note that at “f” in the above sequence, it is possible to leave the BUSY bit at 0. In this case, the master will receive
an ACK instead at “g” and it would still be possible for the I²C master to generate a STOP bit immediately after the
ACK.
Rev 1.0
371