C8051F970-A-GM Datasheet, PDF (172/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
20.6. SFR Page Stack Example
This example demonstrates the operation of the SFR page stack during interrupts. In this example, the SFR control
register is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51 is executing in-line code that is writ-
ing values to I2C0STAT I2C Slave 0 status register (located at address 0xF8 on SFR page 0x0F). The device is
also using the SPI peripheral (SPI0) and the Programmable Counter Array (PCA0) peripheral to generate a PWM
output. The PCA is timing a critical control function in its interrupt service routine, and so its associated ISR is set to
high priority. At this point, the SFR page is set to access the I2C0STAT SFR (SFRPAGE = 0x0F). See Figure 20.3.
0x0F
(I2C0STAT)
SFR Page
Stack SFRs
SFRPAGE
SFRNEXT
SFRLAST
Figure 20.3. SFR Page Stack While Using SFR Page 0x0F To Access I2C0STAT
Rev 1.0
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