C8051F970-A-GM Datasheet, PDF (426/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
33.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the
PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match
occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An interrupt request is generated if the
CCFn interrupt for that module is enabled. The CCFn bit is not automatically cleared by hardware when the CPU
vectors to the interrupt service routine, and must be cleared by software. Setting the TOGn, MATn, and ECOMn
bits in the PCA0CPMn register enables the High-Speed Output mode. If ECOMn is cleared, the associated pin will
retain its state, and not toggle on the next match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare
registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to 0; writing to
PCA0CPHn sets ECOMn to 1.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn ^ENB
1
PCA0CPMn
PECCMT PE
WC A A A O WC
MO P P T GMC
1 MPN n n n F
6nnn
n
n
x 00
0x
PCA Interrupt
PCA0CPLn PCA0CPHn
PCA0CN
CC
CCC
FR
CCC
FFF
210
Enable
16-bit Comparator
PCA
Timebase
PCA0L
PCA0H
Match
Toggle
0
1
TOGn
0 _{CEXn Crossbar}
1
Figure 33.6. PCA High-Speed Output Mode Diagram
Port I/O
Rev 1.0
427