C8051F970-A-GM Datasheet, PDF (379/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 30.5. I2C0CN: I2C0 Control
Bit
7
6
5
Name
Reserved
PUEN
Type
R
RW
Reset
0
0
0
SFR Page = 0xF; SFR Address: 0xAC
4
PINMD
RW
0
3
2
TIMEOUT PRELOAD
RW
RW
0
1
1
I2C0EN
RW
0
0
BUSY
RW
1
Bit
Name
Function
7:6
Reserved Must write reset value.
5
PUEN I2C Pull-Up Enable.
0: Disable internal pull-up resistors for the I2C0 Slave SCL and SDA pins.
1: Enable internal pull-up resistors for the I2C0 Slave SCL and SDA pins.
4
PINMD Pin Mode Enable.
0: Set the I2C0 Slave pins in GPIO mode.
1: Set the I2C0 Slave pins in I2C mode.
3
TIMEOUT Timeout Enable.
When this bit is set, Timer 3 will start counting only when SCL is low. When SCL is high,
Timer 3 will auto-reload with the value from the reload registers. Timer 3 must be config-
ured for 16-bit auto-reload mode.
0: Disable I2C SCL timeout detection using Timer 3.
1: Enable I2C SCL timeout detection using Timer 3.
2
PRELOAD Preload Disable.
0: Data bytes must be written into the I2C0DOUT register before the 8th SCL clock of the
matching slave address byte transfer arrives for an I2C read operation.
1: Data bytes need not be preloaded for I2C read operations. The data byte can be writ-
ten to I2C0DOUT during interrupt servicing or by the DMA.
1
I2C0EN I2C Enable.
This bit enables the I2C0 Slave module. PINMD must be enabled first before this bit is
enabled.
0: Disable the I2C0 Slave module.
1: Enable the I2C0 Slave module.
0
BUSY Busy.
0: Device will acknowledge an I2C master.
1: Device will not respond to an I2C master. All I2C data sent to the device will be
NACKed.
380
Rev 1.0