C8051F970-A-GM Datasheet, PDF (164/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
20. CIP-51 Microcontroller Core
The C8051F97x uses the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set;
standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset
of all the peripherals included with a standard 8051. The CIP-51 also includes on-chip debug hardware and
interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional
custom peripherals and functions to extend its capability (see Figure 20.1 for a block diagram). The CIP-51
includes the following features:
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
20.1. Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard
8051 architecture. The CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no
instructions taking more than eight system clock cycles.
DATA BUS
ACCUMULATOR
TMP1
TMP2
PSW
ALU
B REGISTER
STACK POINTER
SRAM
ADDRESS
REGISTER
SRAM
DATA BUS
BUFFER
D8
DATA POINTER
D8
PC INCREMENTER
SFR_ADDRESS
SFR
SFR_CONTROL
D8
BUS
SFR_WRITE_DATA
INTERFACE
SFR_READ_DATA
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
RESET
CLOCK
CONTROL
LOGIC
PIPELINE
STOP
IDLE
POWER CONTROL
REGISTER
D8
D8
MEM_ADDRESS
MEM_CONTROL
MEMORY
A16
INTERFACE ^{MEM_WRITE_DATA}
MEM_READ_DATA
D8
INTERRUPT
INTERFACE
D8
SYSTEM_IRQs
EMULATION_IRQ
Figure 20.1. CIP-51 Block Diagram
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total
of 109 instructions. The table below shows the total number of instructions that require each execution time.
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1
Rev 1.0
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