C8051F970-A-GM Datasheet, PDF (393/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
32.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in
TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, CT0, GATE0 and TF0. TL0 can
use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer
function sourced by the system clock or prescaled clock. TH0 is enabled using the Timer 1 run control bit TR1. TH0
sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2,
but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1
overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC conversions. While
Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while
Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for Mode 3.
Pre-scaled Clock
SYSCLK
T0M
CT0
0
TR1
1
0
TH0
(8 bits)
TF1
(Interrupt Flag)
1
T0
TR0
GATE0
TCLK
TL0
(8 bits)
TF0
(Interrupt Flag)
INT0
IN0PL _XOR
Figure 32.3. T0 Mode 3 Block Diagram
394
Rev 1.0