C8051F970-A-GM Datasheet, PDF (414/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

32.7. Timer 3 Registers
C8051F97x
Register 32.13. TMR3CN: Timer 3 Control
Bit
7
6
5
4
3
2
1
0
Name TF3H
TF3L
TF3LEN TF3CEN T3SPLIT
TR3
T3XCLK
Type
RW
RW
RW
RW
RW
RW
R
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0x91
Table 32.15. TMR3CN Register Bit Descriptions
Bit
Name
Function
7
TF3H Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16-bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3
interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3 interrupt ser-
vice routine. This bit must be cleared by firmware.
6
TF3L Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will be
set when the low byte overflows regardless of the Timer 3 mode. This bit must be cleared
by firmware.
5
TF3LEN Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are also
enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
4
TF3CEN Timer 3 Capture Enable.
When set to 1, this bit enables Timer 3 Capture Mode. If TF3CEN is set and Timer 3
interrupts are enabled, an interrupt will be generated based on the selected input capture
source, and the current 16-bit timer value in TMR3H:TMR3L will be copied to
TMR3RLH:TMR3RLL.
3
T3SPLIT Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
2
TR3
Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables TMR3H
only; TMR3L is always enabled in split mode.
Rev 1.0
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