C8051F970-A-GM Datasheet, PDF (373/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
30.5.4. I²C Read Sequence (DMA Mode)
I2C0 module – DMA mode – clock stretch – Read
1
Sleep
Active
2
S SLA R A
3
DB0 A
DB1 A
xa
b
c
1 SLA+R wakes CPU from sleep mode.
4
DB2 N Sr SLA R A
d
xe
45
DB3 N P
fg
S = START
P = STOP
A = ACK
N = NACK
R = Read
W = Write
Sr = repeated START
Shaded blocks are generated by
Slave device
2
INT generated. CPU configures DMA for I2C Read. CPU performs SW DMA request to transfer DB0 from XRAM to
I2C0DOUT. SCL is held until CPU clears I2C0INT.
3 DMA transfers DB1 from XRAM to I2C0DOUT and asserts i2c_dma_ack which releases SCL
4
NACK switches I2C slave into IDLE state. Any following DB are ignored. If RpStart follows NACK, the START sticky bit will
be set, but no interrupt.
5 STOP generates interrupt. No Clock Stretch. CPU clears I2C0INT
No int x
I2C0 int a
No int b
No int c
I2C0 int d
I2C0 int e
I2C0 int f
I2C0 int g
I2C0INT = x1001000 at 8^th SCL rising edge
I2C0INT = x1101001; CPU clears START. CPU configures DMA for I2C Read; CPU starts SW DMA to transfer DB0 from
XRAM to I2CDOUT. CPU clears I2C0INT
I2C0STAT = x1000000; DMA transfers DB1 from XRAM to I2C0DOUT
I2C0STAT = x1000000; DMA transfers DB2 from XRAM to I2C0DOUT
I2C0STAT = x0110001; NACK causes I2C to not generate i2c_dma_req. CPU clears I2C0INT, NACK. CPU disables DMA.
I2C0INT = x1101001; CPU clears START. CPU configures DMA for I2C Read; CPU starts SW DMA to transfer DB3 from
XRAM to I2CDOUT. CPU clears I2C0INT
I2C0STAT = x0110001; NACK causes I2C to not generate i2c_dma_req. CPU clears I2C0INT, NACK. CPU disables DMA.
I2C0STAT = x0100100; CPU clears STOP and clears I2C0INT
* At a, d, e, f: Bits are set at 9^th SCL falling edge. SCL released when CPU clear I2C0INT
* At b, c: i2c_dma_req asserted at 9^th SCL falling edge. SCL released by i2c_dma_ack
Figure 30.8. Typical I²C Read Sequence in DMA Mode
374
Rev 1.0