C8051F970-A-GM Datasheet, PDF (246/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
24.4. Special Function Registers for Selecting and Configuring the System Clock
The clocking sources on C8051F97x devices are enabled and configured using the OSCICN, OSCICL, OSCXCN
and the SmaRTClock internal registers. See Section “21. SmaRTClock (Real Time Clock)” on page 292 for
SmaRTClock register descriptions. The system clock source for the MCU can be selected using the CLKSEL
register. To minimize active mode current, the oneshot timer which sets Flash read time should by bypassed when
the system clock is greater than 10 MHz. See the FLSCL register description for details.
The clock selected as the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching between
two clock divide values, the transition may take up to 128 cycles of the undivided clock source. The CLKRDY flag
can be polled to determine when the new clock divide value has been applied. The clock divider must be set to
"divide by 1" when entering Suspend or Sleep Mode.
The system clock source may also be switched on-the-fly. The switchover takes effect after one clock period of the
slower oscillator.
Rev 1.0
247