C8051F970-A-GM Datasheet, PDF (207/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
A few important points to note for DMA mode operation:
Partial DMA transfers will terminate DMA mode operation. For example, a MAC0A DMA transaction
requires 2 bytes, but if the DMA has only 1 byte left to transfer, the DMA mode operation will terminate after
the single byte is transferred into MAC0A.
Even if DMA transfers are enabled for MAC0A, no DMA request will be generated for MAC0A if either
APOSTINC or ADMASRC bit is set to 1.
If the ACCDMAIN field specifies a transfer length of less than 5 bytes, only the least significant bytes of the
accumulator will receive data from the DMA. The upper bytes will be sign-extended in a way that is
compatible with the SIGNEDEN setting as shown in Figure 22.5. The example below shows the result of
the 41-bit accumulator after a transfer of a 16-bit number d[0:15] by DMA.
UnsignedDMAtransferof2bytes(b[0:15]into41Ͳbitaccumulator(MAC0ACCIN_DMA=1)
Bitposition 40 39^ 38^ 37 17 16 15 14 13 2 1 0

0 0^ 0^ 0 0 0 d15 d14 d13 d3 d1 d0

SignedDMAtransferof2bytes(b[0:15]into41Ͳbitaccumulator(MAC0ACCIN_DMA=1)
Bitposition 40 39^ 38^ 37 17 16 15 14 13 2 1 0

d15 d15 d15 d15 d15 d15 d15 d14 d13 d3 d1 d0
Figure 22.5. DMA Transfer into Accumulator in Sign and Unsigned Modes
22.7. Accumulator 1-Bit Shift Operations
MAC0 contains a 1-bit arithmetic shift function which can be used to shift the contents of the 41-bit accumulator left
or right by one bit. The accumulator shift is initiated by writing a 1 to the SHIFTEN bit and takes one SYSCLK cycle
to complete. In MCU mode, setting SHIFTEN bit will immediately shift one bit of the accumulator at the next system
clock regardless of whether the MAC has finished the operation or not. In DMA mode, setting the SHIFTEN bit will
shift the accumulator after the completion of the MAC operation. Hardware automatically clears the SHIFTEN bit to
0 after the shift has completed. The direction of the arithmetic shift is controlled by the SHIFTDIR bit. A 1-bit
arithmetic shift does not affect any flag in the MAC0STA register.
The 1-bit shift examples for signed (SIGNEDEN = 1) and unsigned (SIGNEDEN = 0) modes are shown in
Figure 22.6.
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