C8051F970-A-GM Datasheet, PDF (189/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
21.2.2. DMA0 channel arbitration
Multiple DMA0 channels can request transfer simultaneously, but only one DMA0 channel will be granted the bus
to transfer the data. Channel 0 has the highest priority. DMA0 channels are serviced based on their priority. A
higher priority channel is serviced first. Channel arbitration occurs at the end of the data transfer granularity
(transaction boundary) of the DMA. When there is a DMA0 request at the transaction boundary from higher priority
channel, lower priority ones will be stalled until the highest priority one completes its transaction. So, for 16-bit
transfers like MAC0AH:L, the transaction boundary is at every 2 bytes.
21.3. DMA0 Operation in Low Power Modes
DMA0 remains functional in normal active, low power active, idle, low power idle modes but not in sleep or
suspend mode. CPU will wait for DMA0 to complete all pending requests before it enters sleep mode. When the
system wakes up from suspend or sleep mode to normal active mode, pending DMA0 interrupts will be serviced
according to priority of channels. DMA0 stalls when CPU is in debug mode.
21.4. Transfer Configuration
The following steps are required to configure one of the DMA0 channels for operation:
1. Select the channel to be configured by writing DMA0SEL.
2. Specify the data transfer function by writing DMA0NCF. This register also specifies the endianness of the
data in XRAM and enables full or mid-point interrupts.
3. Specify the base address in XRAM for the transfer by writing DMA0NBAH:L.
4. Specify the size of the transfer in bytes by writing DMA0NSZH:L.
5. Reset the address offset counter by writing 0 to DMA0NAOH:L.
6. Enable the DMA0 channel by writing 1 to the appropriate bit in DMA0EN.
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