C8051F970-A-GM Datasheet, PDF (72/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 10.3. FLSCL: Flash Scale
Bit
7
6
5
4
3
2
1
0
Name Reserved BYPASS
Reserved
Type
R
RW
R
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0xB6
Table 10.4. FLSCL Register Bit Descriptions
Bit
Name
Function
7
Reserved Must write reset value.
6
BYPASS Flash Read Timing One-Shot Bypass.
0: The one-shot determines the flash read time. This setting should be used for operating
frequencies less than 14 MHz.
1: The system clock determines the flash read time. This setting should be used for fre-
quencies greater than 14 MHz.
5:0
Reserved Must write reset value.
Note: Operations which clear the BYPASS bit do not need to be immediately followed by a benign 3-byte instruction. For
code compatibility with C8051F930/31/20/21 devices, a benign 3-byte instruction whose third byte is a don't care
should follow the clear operation. See the C8051F93x-C8051F92x data sheet for more details.
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Rev 1.0