C8051F970-A-GM Datasheet, PDF (386/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

31.4. UART Control Registers
C8051F97x
Register 31.1. SCON0: UART0 Serial Port Control
Bit
7
6
5
4
3
2
1
0
Name SMODE Reserved MCE
REN
TB8
RB8
TI
RI
Type
RW
R
RW
RW
RW
RW
RW
RW
Reset
0
1
0
0
0
0
0
0
SFR Page = ALL; SFR Address: 0x98 (bit-addressable)
Table 31.2. SCON0 Register Bit Descriptions
Bit
Name
Function
7
SMODE Serial Port 0 Operation Mode.
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate (Mode 0).
1: 9-bit UART with Variable Baud Rate (Mode 1).
6
Reserved Must write reset value.
5
MCE Multiprocessor Communication Enable.
This bit enables checking of the stop bit or the 9th bit in multi-drop communication buses.
The function of this bit is dependent on the UART0 operation mode selected by the
SMODE bit. In Mode 0 (8-bits), the peripheral will check that the stop bit is logic 1. In
Mode 1 (9-bits) the peripheral will check for a logic 1 on the 9th bit.
0: Ignore level of 9th bit / Stop bit.
1: RI is set and an interrupt is generated only when the stop bit is logic 1 (Mode 0) or
when the 9th bit is logic 1 (Mode 1).
4
REN Receive Enable.
0: UART0 reception disabled.
1: UART0 reception enabled.
3
TB8
Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
2
RB8
Ninth Receive Bit.
RB8 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th
data bit in Mode 1.
1
TI
Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in
8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the
UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 inter-
rupt service routine. This bit must be cleared manually by firmware.
Rev 1.0
387