C8051F970-A-GM Datasheet, PDF (328/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
28. Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can
operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a
single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode, or to
disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than
one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master
mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple
slave devices in master mode.
SYSCLK
SPI0
SCK Phase
SCK Polarity
Master or Slave
NSS Control
Clock Rate
Generator
Bus Control
Shift Register
TX Buffer RX Buffer
SPI0DAT
NSS
SCK
MISO
MOSI
Figure 28.1. SPI0 Block Diagram
Rev 1.0
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