C8051F970-A-GM Datasheet, PDF (116/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 17.3. ADC0AC: ADC0 Accumulator Configuration
Bit
7
6
5
4
3
2
1
0
Name Reserved ADAE
ADSJST
ADRPT
Type
RW
W
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address: 0xBA
Table 17.4. ADC0AC Register Bit Descriptions
Bit
Name
Function
7
Reserved Must write reset value.
6
ADAE Accumulate Enable.
Enables multiple conversions to be accumulated when burst mode is disabled. This bit is
write-only and always reads as zero.
0: ADC0H:ADC0L contain the result of the latest conversion when Burst Mode is dis-
abled.
1: ADC0H:ADC0L contain the accumulated conversion results when Burst Mode is dis-
abled. Firmware must write 0x0000 to ADC0H:ADC0L to clear the accumulated result.
5:3
ADSJST Accumulator Shift and Justify.
Specifies the format of data read from ADC0H:ADC0L. All remaining bit combinations
are reserved.
000: Right justified. No shifting applied.
001: Right justified. Shifted right by 1 bit.
010: Right justified. Shifted right by 2 bits.
011: Right justified. Shifted right by 3 bits.
100: Left justified. No shifting applied.
101-111: Reserved.
2:0
ADRPT Repeat Count.
Selects the number of conversions to perform and accumulate in Burst Mode. This bit
field must be set to 000 if Burst Mode is disabled.
000: Perform and Accumulate 1 conversion.
001: Perform and Accumulate 4 conversions.
010: Perform and Accumulate 8 conversions.
011: Perform and Accumulate 16 conversions.
100: Perform and Accumulate 32 conversions.
101: Perform and Accumulate 64 conversions.
110-111: Reserved.
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Rev 1.0