C8051F970-A-GM Datasheet, PDF (110/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
17.3.4. Settling Time Requirements
A minimum amount of tracking time is required before each conversion can be performed, to allow the sampling
capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling
capacitance, any external source resistance, and the accuracy required for the conversion. Note that in low-power
tracking mode, three SAR clocks are used for tracking at the start of every conversion. For many applications,
these three SAR clocks will meet the minimum tracking time requirements, and higher values for the external
source impedance will increase the required tracking time.
Figure 17.4 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling accuracy
(SA) may be approximated by Equation 17.1. When measuring the Temperature Sensor output or V_DD with respect
to GND, R_TOTAL reduces to R_MUX. See Table 1.11 for ADC0 minimum settling time requirements as well as the mux
impedance and sampling capacitor values.
Where
t
=
ln


S^-2---A^{-n-}

R_TOTALC_SAMPLE
SA is the settling accuracy, given as a fraction of an LSB (e.g., 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R_TOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10)
Equation 17.1. ADC0 Settling Time Requirements
MUX Select
P0.x
R_MUX
RC_Input= R_MUX * C_SAMPLE
C_SAMPLE
Note: The value of CSAMPLE depends on the PGA Gain. See Table 1.11 for details.
Figure 17.4. ADC0 Equivalent Input Circuits
17.3.5. Gain Setting
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined directly by
V_REF. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is V_REF x 2. The 0.5x gain
setting can be useful to obtain a higher input Voltage range when using a small V_REF voltage, or to measure input
voltages that are between V_REF and V_DD. Gain settings for the ADC are controlled by the AMP0GN bit in register
ADC0CF.
17.4. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode. In 8-bit mode, only the 8 MSBs of
data are converted, allowing the conversion to be completed in two fewer SAR clock cycles than a 10-bit
conversion. This can result in an overall lower power consumption since the system can spend more time in a low
power mode. The two LSBs of a conversion are always 00 in this mode, and the ADC0L register will always read
back 0x00.
110
Rev 1.0