C8051F970-A-GM Datasheet, PDF (378/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Bit
Name
Function
0
RD
I2C Read.
This bit is set by hardware on the 9th SCL falling edge when one of the following condi-
tions are met:
- The I2C Master responds with an ACK, and the DMA has not enabled I2C0 Slave Read
as a data transfer function.
- I2C Master responds with a NACK.
- The current byte transaction has a matching I2C slave address and the 8th bit was a
READ bit (1).
This bit will set the I2C0INT bit and generate an interrupt, if enabled. Hardware will auto-
matically clear this bit.
Rev 1.0
379