C8051F970-A-GM Datasheet, PDF (431/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
33.4. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used to
generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified limit. The
WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 2 operates as a watchdog timer (WDT). The Module 2 high
byte is compared to the PCA counter high byte; the Module 2 low byte holds the offset to be used when WDT
updates are performed. The Watchdog Timer is enabled on reset. Writes to some PCA registers are
restricted while the Watchdog Timer is enabled. The WDT will generate a reset shortly after code begins
execution. To avoid this reset, the WDT should be explicitly disabled (and optionally re-configured and re-enabled if
it is used in the system).
33.4.1. Watchdog Timer Operation
While the WDT is enabled:
 PCA counter is forced on.
 Writes to PCA0L and PCA0H are not allowed.
 PCA clock source bits (CPS2–CPS0) are frozen.
 PCA Idle control bit (CIDL) is frozen.
 Module 2 is forced into software timer mode.
 Writes to the Module 2 mode register (PCA0CPM2) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run until the
WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but user software has
not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while the WDT is enabled, a
reset will be generated. To prevent a WDT reset, the WDT may be updated with a write of any value to
PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is loaded into PCA0CPH2 (See
Figure 33.11).
PCA0MD
CWW CCCE
I DD PPPC
DTL SSSF
LEC 2 1 0
K
PCA0CPH2
8-bit
Match
Reset
Enable ^Comparator
PCA0CPL2
8-bit Adder
PCA0H
PCA0L Overflow
Write to
PCA0CPH2
Adder
Enable
Figure 33.11. PCA Module 2 with Watchdog Timer Enabled
The 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset value is the
number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first PCA0L overflow
occurs, depending on the value of the PCA0L when the update is performed. The total offset is then given (in PCA
clocks) by Equation 33.5, where PCA0L is the value of the PCA0L register at the time of the update.
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