C8051F970-A-GM Datasheet, PDF (193/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 21.4. DMA0BUSY: DMA0 Busy
Bit
7
6
5
4
3
2
1
0
Name Reserved CH6BUSY CH5BUSY CH4BUSY CH3BUSY CH2BUSY CH1BUSY CH0BUSY
Type
R
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address: 0x91
Bit
Name
Function
7
Reserved Must write reset value.
6
CH6BUSY Channel 6 Busy.
This bit is set to 1 by hardware when a DMA0 transfer is in progress on channel 6. Writ-
ing this bit to 1 forces a DMA0 transfer to start on channel 6.
5
CH5BUSY Channel 5 Busy.
This bit is set to 1 by hardware when a DMA0 transfer is in progress on channel 5. Writ-
ing this bit to 1 forces a DMA0 transfer to start on channel 5.
4
CH4BUSY Channel 4 Busy.
This bit is set to 1 by hardware when a DMA0 transfer is in progress on channel 4. Writ-
ing this bit to 1 forces a DMA0 transfer to start on channel 4.
3
CH3BUSY Channel 3 Busy.
This bit is set to 1 by hardware when a DMA0 transfer is in progress on channel 3. Writ-
ing this bit to 1 forces a DMA0 transfer to start on channel 3.
2
CH2BUSY Channel 2 Busy.
This bit is set to 1 by hardware when a DMA0 transfer is in progress on channel 2. Writ-
ing this bit to 1 forces a DMA0 transfer to start on channel2.
1
CH1BUSY Channel 1 Busy.
This bit is set to 1 by hardware when a DMA0 transfer is in progress on channel 1. Writ-
ing this bit to 1 forces a DMA0 transfer to start on channel 1.
0
CH0BUSY Channel 0 Busy.
This bit is set to 1 by hardware when a DMA0 transfer is in progress on channel 0. Writ-
ing this bit to 1 forces a DMA0 transfer to start on channel 0.
194
Rev 1.0