C8051F970-A-GM Datasheet, PDF (151/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 18.9. CS0MD1: Capacitive Sense 0 Mode 1
Bit
7
6
5
4
3
2
1
0
Name Reserved CS0POL
CS0DR
CS0WOI
CS0CG
Type
RW
R
R
R
RW
Reset
0
0
0
0
0
1
1
1
SFR Page = 0x0; SFR Address: 0xBD
Bit
Name
Function
7
Reserved Must write reset value.
6
CS0POL CS0 Digital Comparator Polarity Select.
0: The digital comparator generates an interrupt if the conversion is greater than the
threshold.
1: The digital comparator generates an interrupt if the conversion is less than or equal to
the threshold.
5:4
CS0DR CS0 Double Reset Select.
These bits adjust the secondary CS0 reset time. For most touch-sensitive switches, the
default (fastest) value is sufficient.
00: No additional time is used for secondary reset.
01: An additional 0.75 us is used for secondary reset.
10: An additional 1.5 us is used for secondary reset.
11: An additional 2.25 us is used for secondary reset.
3
CS0WOI CS0 Wake on Interrupt Configuration.
0: Wake-up event generated on digital comparator interrupt only.
1: Wake-up event generated on end of scan or digital comparator interrupt.
2:0
CS0CG CS0 Capacitance Gain Select.
These bits select the gain applied to the capacitance measurement. Lower gain values
increase the size of the capacitance that can be measured with the CS0 module. The
capacitance gain is equivalent to CS0CG[2:0] + 1.
000: Gain = 1x
001: Gain = 2x
010: Gain = 3x
011: Gain = 4x
100: Gain = 5x
101: Gain = 6x
110: Gain = 7x
111: Gain = 8x
Rev 1.0
151