C8051F970-A-GM Datasheet, PDF (85/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 13.3. EIE1: Extended Interrupt Enable 1
Bit
7
6
5
4
3
2
1
0
Name
ET3
EDMA0 EDMA0M EPCA0 EADC0 EWADC0 ERTC0A ESMB0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Page = ALL; SFR Address: 0xE6
Table 13.4. EIE1 Register Bit Descriptions
Bit
Name
Function
7
ET3
Timer 3 Interrupt Enable.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
6
EDMA0 DMA0 Interrupt Enable.
This bit sets the masking of the DMA0 Interrupt.
0: Disable DMA0 interrupts.
1: Enable interrupt requests generated by DMA0.
5
EDMA0M DMA0 Mid-Point Interrupt Enable.
This bit sets the masking of the DMA0 Mid-Point interrupt.
0: Disable DMA0M interrupts.
1: Enable interrupt requests generated by the DMA0M flags.
4
EPCA0 Programmable Counter Array (PCA0) Interrupt Enable.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
3
EADC0 ADC0 Conversion Complete Interrupt Enable.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the ADINT flag.
2
EWADC0 Window Comparison ADC0 Interrupt Enable.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (ADWINT).
1
ERTC0A RTC Alarm Interrupts Enable.
This bit sets the masking of the RTC Alarm interrupt.
0: Disable RTC Alarm interrupts.
1: Enable interrupt requests generated by a RTC Alarm.
Rev 1.0
85