C8051F970-A-GM Datasheet, PDF (191/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 21.2. DMA0INT: DMA0 Full-Length Interrupt Flags
Bit
7
6
5
4
Name Reserved CH6I
CH5I
CH4I
Type
R
RW
RW
RW
Reset
0
0
0
0
SFR Page = 0xF; SFR Address: 0xE8 (bit-addressable)
3
CH3I
RW
0
2
CH2I
RW
0
1
CH1I
RW
0
0
CH0I
RW
0
Bit
Name
Function
7
Reserved Must write reset value.
6
CH6I Channel 6 Full-Length Interrupt Flag.
0: No Interrupt generated.
1: Full-length interrupt generated in channel 6.
5
CH5I Channel 5 Full-Length Interrupt Flag.
0: No Interrupt generated.
1: Full-length interrupt generated in channel 5.
4
CH4I Channel 4 Full-Length Interrupt Flag.
0: No Interrupt generated.
1: Full-length interrupt generated in channel 4.
3
CH3I Channel 3 Full-Length Interrupt Flag.
0: No Interrupt generated.
1: Full-length interrupt generated in channel 3.
2
CH2I Channel 2 Full-Length Interrupt Flag.
0: No Interrupt generated.
1: Full-length interrupt generated in channel 2.
1
CH1I Channel 1 Full-Length Interrupt Flag.
0: No Interrupt generated.
1: Full-length interrupt generated in channel 1.
0
CH0I Channel 0 Full-Length Interrupt Flag.
0: No Interrupt generated.
1: Full-length interrupt generated in channel 0.
Note: Channel full-length interrupt flags are set when the offset address DMA0NAOH/L equals to data transfer size
DMA0NSZH/L minus 1 for the channel. Firmware must clear this flag. The full-length interrupt is enabled by setting the
IEN bit in the DMA0NCF register with DMA0SEL configured for the corresponding channel.
192
Rev 1.0