C8051F970-A-GM Datasheet, PDF (303/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
Register 26.19. P2: Port 2 Pin Latch
Bit
7
6
5
4
3
2
1
0
Name
B7
B6
B5
B4
B3
B2
B1
B0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
1
1
1
1
1
1
1
1
SFR Page = ALL; SFR Address: 0xA0 (bit-addressable)
Table 26.22. P2 Register Bit Descriptions
Bit
Name
Function
7
B7
Port 2 Bit 7 Latch.
0: P2.7 is low. Set P2.7 to drive low.
1: P2.7 is high. Set P2.7 to drive or float high.
6
B6
Port 2 Bit 6 Latch.
0: P2.6 is low. Set P2.6 to drive low.
1: P2.6 is high. Set P2.6 to drive or float high.
5
B5
Port 2 Bit 5 Latch.
0: P2.5 is low. Set P2.5 to drive low.
1: P2.5 is high. Set P2.5 to drive or float high.
4
B4
Port 2 Bit 4 Latch.
0: P2.4 is low. Set P2.4 to drive low.
1: P2.4 is high. Set P2.4 to drive or float high.
3
B3
Port 2 Bit 3 Latch.
0: P2.3 is low. Set P2.3 to drive low.
1: P2.3 is high. Set P2.3 to drive or float high.
2
B2
Port 2 Bit 2 Latch.
0: P2.2 is low. Set P2.2 to drive low.
1: P2.2 is high. Set P2.2 to drive or float high.
1
B1
Port 2 Bit 1 Latch.
0: P2.1 is low. Set P2.1 to drive low.
1: P2.1 is high. Set P2.1 to drive or float high.
0
B0
Port 2 Bit 0 Latch.
0: P2.0 is low. Set P2.0 to drive low.
1: P2.0 is high. Set P2.0 to drive or float high.
Notes:
1. Writing this register sets the port latch logic value for the associated I/O pins configured as digital I/O.
2. Reading this register returns the logic value at the pin, regardless if it is configured as output or input.
304
Rev 1.0