C8051F970-A-GM Datasheet, PDF (397/454 Pages) Silicon Laboratories – Low Power Capacitive Sensing MCU with up to 32 kB of Flash

C8051F97x
32.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate
in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit in the TMR3CN register defines the
Timer 3 operation mode. Timer 3 can also be used in Capture Mode to measure the external oscillator source or
the SmaRTClock oscillator period with respect to another oscillator.
Timer 3 may be clocked by the system clock, the system clock divided by 12, external oscillator source divided by
8, or the SmaRTClock oscillator. The external oscillator source divided by 8 and SmaRTClock oscillator is synchro-
nized with the system clock.
32.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT in the TMR3CN register is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, external oscillator clock source divided by 8, or SmaRTClock oscilla-
tor. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3
reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in Figure 32.7, and the
Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled (if EIE1.7 is set), an interrupt
will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled and the TF3LINT bit is
set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L) overflow from 0xFF to 0x00.
T3XCLK[1:0]
SYSCLK / 12
00
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
To ADC
External Clock / 8
SmaRTClock
01
11
SYSCLK
0
TR3
1
TCLK _{TMR3L TMR3H}
TMR3RLL TMR3RLH
Reload
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK1
T3XCLK0
Figure 32.7. Timer 3 16-Bit Mode Block Diagram
Interrupt
398
Rev 1.0